The present invention pertains to digital switching circuits and, more particularly, to reducing power dissipation in a flip-flop circuit.
In large modern digital designs, a very common and useful circuit is the flip-flop, which is herein defined to mean any bi-stable circuit having the below described problems incorporated therein. The purpose of a flip-flop is to latch a data value which is present at its input at a time t.sub.1, to its output at a later time t.sub.2. The latching activity is driven by a clock signal which typically operates at a global clock frequency on the order of megahertz (MHz). The latching mechanism typically requires the clock signal and its complement, hence, a chain of inverters is used to generate these signals internal to the flip-flop.
The total power dissipation (P.sub.TOTAL) in CMOS circuits is comprised of power due to the charging/discharging of capacitive loads (P.sub.CAP), short circuit power (P.sub.SH) due to short circuit current when transistors switch, and leakage power (P.sub.IDD) due to static leakage current. In particular, the total power for a circuit can be calculated using the following equations: EQU P.sub.TOTAL =P.sub.CAP +P.sub.SH +P.sub.IDD EQU P.sub.CAP =C.sub.L V.sub.DD.sup.2 f ##EQU1## EQU P.sub.IDD =I.sub.DD V.sub.DD
where:
C.sub.L is the capacitive loading at an output of the circuit,
V.sub.DD is the supply voltage, PA1 f is the frequency of the output (1/T, where T is the cycle time), PA1 I.sub.SH is the short circuit current, and PA1 I.sub.DD is the leakage current of the circuit.
The majority of the total power in typical CMOS circuits is due to the capacitive power (P.sub.CAP), a smaller portion is due to the short circuit power (P.sub.SH), and a negligible amount is due to the leakage power (P.sub.IDD). The power due to the charging/discharging of capacitive loads (P.sub.CAP) occurs when the flip-flop is clocked. The continuous clocking of the flip-flop, even when no new data is present, consumes unnecessary power.
Accordingly, it is desirable to reduce total power dissipation in a flip-flop circuit.